circuit technology www.aeroflex.com eroflex circuit technology - advanced multichip modules ? scd3764 rev a 6/2/98 general description the act-ps512k8 is a plastic high speed, 4 megabit (4,194,304 bits) cmos monolithic sram organized as 524,288 words by 8 bits. designed for high-speed, high density, high reliablility, mass memory and fast cache system applications. the plastic monolithic is input and output ttl compatible.writingisexecuted when the write enable ( we ) and chip enable ( ce ) inputs are low. reading is accomplished when we is high and ce and output enable ( oe ) are both low. access time grades of 10ns 12ns, 15ns, 17ns, 20ns and 25ns are standard. 512kx8 oe a 0 ? a 18 i/o 0-7 8 we ce pin description i/o 0-7 data i/o a 0?18 address inputs we write enable ce chip enable oe output enable v c c power supply v ss ground nc not connected v ss v cc block diagram ? soj (l2) plastic path? features n low power monolithic cmos 512k x 8 sram n operating temperature range l full military (-55c to +125c) l industrial (-40c to +85c) n burn-in and temperature cycle available n 10, 12, 15, 17, 20 & 25ns access times n +5v power supply n industry standard pinouts l center power / ground pins n ttl compatible i/o n 3.3v device i/o interfacing n jedec standard 36 pin plastic soj package l 36 lead, .93" x .405" x 0.148 small outline j lead (soj), aeroflex code# "l2" n fully static operation l no clocks or refresh required 4 megabit plastic monolithic sram act-ps512k8 high speed f i e i d c e r t a e r o f l e x l a b s i n c . iso 900 1
aeroflex circuit technology scd3764 rev a 6/2/98 plainview ny (516) 694-6700 2 absolute maximum ratings symbol parameter minimum maximum units t c case operating temperature -55 +125 c t stg storage temperature -65 +150 c p d maximum package power dissipation 1.0 w v g maximum signal voltage to ground -0.5 v cc + 0.5 v v cc power supply voltage -0.5 +7.0 v recommended operating conditions symbol parameter minimum maximum units v cc power supply voltage +4.5 +5.5 v v ss ground 0 0 v v ih input high voltage +2.2 v cc + 0.5 v v il input low voltage -0.5 +0.8 v t c operating temperature (military) -55 +125 c t c operating temperature (industrial) -40 +85 c truth table mode ce we oe data i/o supply current standby h x x high z i sb output disable l h h high z i cc read l h l data out i cc write l l x data in i cc capacitance (v in & v out = 0v, f = 1mhz, t c = 25c, unless otherwise noted, guaranteed but not tested ) symbol parameter maximum units c in input capacitance (a 0-18 , we & oe ) 6 pf c out output capacitance (i/o 0-7 & ce) 8 pf dc characteristics (v c c = 5.0v, v s s = 0v, t c = -55c to +125c or -40c to +85c) parameter sym conditions min max units input leakage current i li v cc = max, v in =v ss tov cc -10 +10 a output leakage current i lo ce = v ih , oe = v ih , v out = v ss tov cc -10 +10 a operating supply current i cc ce = v il , oe = v ih ,f=5mhz,vcc=5.5v 130 ma standby current i sb ce = v ih , oe = v ih , f=5mhz,vcc=5.5v 20 ma output low voltage v ol i ol = 8 ma, vcc = 4.5v 0.4 v output high voltage v oh i oh = -4 ma, vcc = 4.5v 2.4 v note: dc test conditions: v i l = 0.3v, v i h = vcc - 0.3v.
aeroflex circuit technology scd3764 rev a 6/2/98 plainview ny (516) 694-6700 3 ac characteristics (v c c = 5.0v, v s s = 0v, t c = -55c to +125c or -40c to +85c) read cycle parameter sym ?010 min max ?012 min max ?015 min max ?017 min max ?020 min max ?025 min max units read cycle time t rc 10 12 15 17 20 25 ns address access time t aa 10 12 15 17 20 25 ns chip enable access time t ace 10 12 15 17 20 25 ns output hold from address change t oh 3 3 3 3 4 5 ns output enable to output valid t oe 5 6 7 8 10 12 ns chip enable to output in low z (1) t clz 3 3 3 3 3 3 ns output enable to output in low z (1) t olz 0 0 0 0 0 0 ns chip deselect to output in high z (1) t chz 5 6 7 7 8 10 ns output disable to output in high z (1) t ohz 5 6 7 7 8 10 ns note 1. guaranteed by design, but not tested write cycle parameter sym ?010 min max ?012 min max ?015 min max ?017 min max ?020 min max ?025 min max units write cycle time t wc 10 12 15 17 20 25 ns chip enable to end of write t cw 7 8 10 12 13 15 ns address valid to end of write t aw 7 8 10 12 13 15 ns data valid to end of write t dw 5 6 8 8 9 10 ns write pulse width t wp 7 8 10 12 13 15 ns address setup time t as 0 0 0 0 0 0 ns address hold time t ah 0 0 0 0 0 0 ns output active from end of write (1) t ow 3 3 3 3 4 5 ns write to output in high z (1) t whz 5 6 7 8 8 10 ns data hold from write time t dh 0 0 0 0 0 0 ns note 1. guaranteed by design, but not tested data retention electrical characteristics (special order only) v c c = 5.0v, v s s = 0v, t c = -55c to +125c or -40c to +85c) parameter sym test conditions all speeds min typ max units v cc for data retention v dr ce 3 v cc ? 0.2v 2 5.5 v data retention current i ccdr1 v cc = 3v 0.5 2.0 ma
aeroflex circuit technology scd3764 rev a 6/2/98 plainview ny (516) 694-6700 4 timing diagrams ? sram d i/o t rc t oh t aa data valid previous data valid t o e high z t o h z read cycle timing diagrams data valid t c l z sce oe t a c e t c h z undefined don?t care read cycle 2 ( swe = v i h ) write cycle ( sce controlled, oe = v i h ) t c w t a s t w p t d w t o w sce swe data valid write cycle ( swe controlled, oe = v i h ) d i/o ac test circuit i o l parameter typical units input pulse level 0 ? 3.0 v input rise and fall 5 ns input and output timing reference level 1.5 v notes: 1) v z is programmable from -2v to +7v. 2) i o l and i o h programmable from 0 to 16 ma. 3) tester impedance z o =75 w. 4) v z is typically the midpoint of v o h and v o l . 5) i o l and i o h are adjusted to simulate a typical resistance load circuit. 6) ate tester includes jig capacitance. i o h to device under test v z ~ 1.5 v (bipolar supply) current source current source c l = 50 pf t w c t a w t a h t rc t a a t o l z s e e n o t e s e e n o t e s e e n o t e s e e n o t e note: guaranteed by design, but not tested. d i/o t d h t w h z s e e n o t e read cycle 1 ( sce = oe = v i l , swe = v i h ) write cycle timing diagrams t w p t d w data valid t w c t a w t a h d i/o t d h sce swe t c w t a s a 0-18 a 0-18 a 0-18 a 0-18 ac test conditions
aeroflex circuit technology scd3764 rev a 6/2/98 plainview ny (516) 694-6700 5 pin numbers & functions 36 pins ? soj pin # function pin # function 1 a 0 19 nc 2 a 1 20 a 10 3 a 2 21 a 11 4 a 3 22 a 12 5 a 4 23 a 13 6 ce 24 a 14 7 i/o 0 25 i/o 4 8 i/o 1 26 i/o 5 9 v c c 27 v c c 10 v s s 28 v s s 11 i/o 2 29 i/o 6 12 i/o 3 30 i/o 7 13 we 31 oe 14 a 5 32 a 15 15 a 6 33 a 16 16 a 7 34 a 17 17 a 8 35 a 18 18 a 9 36 nc all dimensions in inches dimensions in inches (.xxx) package outline "l2" ? soj package, 36 leads 11.30 (.445) 11.05 (.435) 9.65 (.380) 9.14 (.360) .69 (.027) 23.62 (.930) 23.37 (.920) 10.29 (.405) 10.03 (.395) 0.95 (.037) 1.27 (.050) .43 (.017 3.76 (.148) max dimensions in millmeters mm 1 18 19 36 min typ +.10 -.05 +.004) -.002) typ .004 max
aeroflex circuit technology scd3764 rev a 6/2/98 plainview ny (516) 694-6700 6 ordering information (typical) model number options speed package act-ps512k8n?010l2i none 10ns 36 lead soj act-ps512k8w?012l2i burn-in 12ns 36 lead soj act-ps512k8x?015l2t temp cycle 15ns 36 lead soj act-ps512k8y?017l2t temp cycle & burn-in 17ns 36 lead soj act-ps512k8y?020l2t temp cycle & burn-in 20ns 36 lead soj act-ps512k8y?025l2t temp cycle & burn-in 25ns 36 lead soj 010 = 10ns 012 = 12ns 015 = 15ns 017 = 17ns 020 = 20ns 025 = 25ns aeroflex circuit technology * screened to the test methods of mil-std-883 aeroflex circuit technology 35 south service road plainview new york 11830 telephone: (516) 694-6700 fax: (516) 694-6715 toll free inquiries: 1-(800) 843-1553 circuit technology \\\ act- p s 512k 8 n? 010 l2 t memory type s = plastic sram memory depth, locations options memory width, bits n = none w = burn-in * x = temperature cycle * y = burn-in & temperature cycle * memory speed, ns package type & size l2 = 36 pin plastic soj electrical testing i = industrial temp, -40c to +85c t = military temp, -55c to +125c plastic path part number breakdown
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